Device-Circuit Level Simulation Study of Three Inputs Complex Logic Gate Designed Using Nano-MOSFETs

Ooi Chek Yee

Abstract

Simulation study on silicon-based nano-MOSFETs logic circuits is needed to add more knowledge on the nanoscale circuit performance. Therefore, in this paper, simulation study is carried out on three inputs complex logic gate transistor circuits with four different logic families, namely (i) nano-CMOS complex gate, (ii) nano-MOSFET loaded n-type nano-MOSFET complex gate, (iii) resistive loaded 733.8 Ω nano-MOSFET complex gate, and (iv) pseudo n-type nano-MOSFET complex gate. NanoMOS is used to perform device simulation whereas WinSpice is used to perform circuit simulation. The difficulty faced during downscaling of nano-MOSFET is the realisation of low power high speed nano-MOSFET logic circuits design. Simulation output timing waveforms are used to analyse the timing characteristics of these complex logic circuits with Boolean expression. Transient analysis on nano-MOSFET loaded n-type nano-MOSFET complex gate shows that theoretical modelling calculation of propagation delay and simulated propagation delay is 80% matched. With 10 nm nano-MOSFET complex logic circuits design, dynamic power reduction of 498 times and propagation delay improvement of 20 times are achieved when compared with a typical 120 nm MOSFET logic circuit.

Keywords

Complex gate; Logic family; Nano-MOSFET; Simulation; Theory.

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