Benchmarking Study of Ballistic Current Transport Equations in Symmetric Double-Gate nano-MOSFET by Using Numerical Calculations and Simulation

Ooi Chek Yee


Five electron transport models for drain current equations of symmetric 10 nm Silicon-based (Si-based) double-gate (DG) nano-MOSFET have been numerically investigated in this paper. All these models are based on ballistic transport flow. The first model, named full ballistic model, assumed no backscattering to the source and produced an on-state drain current of 1.137x103 μA/μm. The second model, named electrostatic model which based on electrostatic, included scattering and produced on-state drain current of 2.182x103 μA/μm. Whereas the third model, named flux-theory model, and fourth model, named flux-theory corrected model, were analyzed using flux-theory concept of electron flow and then two different drain current equations were obtained. However, both models producing almost the same value of on-state drain current 2.548x103 μA/μm numerically. Finally, the fifth model, named space charge model, utilized the concept of subband and electron charge distribution on k-space, producing on-state current of 2.241x103 μA/μm. All these models treat electron flow quantum mechanically. Thus, all five computed on-state currents were benchmarked against an on-state current simulated using online device simulator nanoMOS which outputted Si-based ultra-thin channel nano-MOSFET norminal on-state drain current of 2.500x103 μA/μm. The flux-theory models are found to be the most compatible to simulation result because flux-theory model can be generalized for multi-subband, various materials and arbitrary wafer orientations. On the other hand, the first model without backscattering consideration exhibited the least accurate result due to the fact that scattering cannot be ignored in formulating quantum ballistic transport models. The accuracy of this benchmarking evaluation showed that highly sophisticated electron transport numerical models must incorporated ballistic quantum nature effects as well as scattering effects when developing commercial device simulation tools such as TCAD.


Current equation; Electron transport; Nano-MOSFET; Quantum effects; Scattering.

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Qiang Chen, Bhavna Agrawal and James D. Meindl, A comprehensive analytical subthreshold swing (S) model for double-gate MOSFETs, IEEE Transactions on Electron Devices, 49(6), 2022, 1086-1090.

Shaweta Gulati, Jalpaben D. Pandya and Sandhya Save, Performance evaluation of 30 nm double gate MOSFET using VTCAD tool, International Journal of Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering, 2018, 1-8.

Saurabh Mittal and Ashutosh Nandi, Analysis of MC model & DD model on DG-MOSFET for different gate length with different gate oxide, Proceedings of the Second International Conference on Intelligent Computing and Control Systems (ICICCS 2018), Madurai, India, 2018, 817-820.

Kerim Yilmaz, Atieh Farokhnejad, Francisco Criado, Benjamin Iniguez, Francois Lime and Alexander Kloes, Direct source-to-drain tunneling current in ultra-short channel DG MOSFETs by wavelet transform, 2020 IEEE Latin America Electron Devices Conference (LAEDC), San Jose, Costa Rica, 2020.

Hak Kee Jung and Sima Dimitrijev, Analysis of subthreshold carrier transport for ultimate DGMOSFET, IEEE Transactions on Electron Devices, 53(4), 2006, 685-691.

Ashok Kumar Suhag and Rakesh Sharma, Design and simulation of nanoscale double gate MOSFET using high K material and ballistic transport method, Materials Today: Proceedings 4, 2017, 10412-10416.

Kerim Yilmaz, Ghader darbandy, Benjamin Iniguez, Francois Lime and Alexander Kloes, Equivalent length concept for compact modeling of short-channel GAA and DG MOSFETs, 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Grenoble, France, 2019.

Md. Rokib Hasan, Influence of device performance of sub-10 nm GaN-based DG-MOSFET over conventional Si-based SG-MOSFETs, Proceedings of the 2017 4th International Conference on Advances in Electrical Engineering, Dhaka, Bangladesh, 2017, 697-702.

Priyanka Saha, Pritha Banerjee, Dinesh Kumar Dash and Subir Kumar Sarkar, Modeling short channel behavior of proposed work function engineered high-k gate stack DG MOSFET with vertical Gaussian doping, 2018 IEEE Electron Device Kolkata Conference (EDKCON), Kolkata, India, 2018, 32-36.

Ramesh Vaddi, R. P. Agarwal and S. Dasgupta, Compact modeling of a generic double-gate MOSFET with gate-S/D underlap for subthreshold operation, IEEE Transactions on Electron Devices, 59(10), 2012, 2846-2849.

Changwook Jeong, Dimitri Antoniadis and Mark S. Lundstrom, On backscattering and mobility in nanoscale silicon MOSFETs, IEEE Transactions on Electron Devices, 56(11), 2009, 2762-2769.

Fei Yu, Gongyi Huang, Wei Lin and Chuanzhong Xu, An analytical drain current model for symmetric double-gate MOSFETs, AIP Advances, 8, 2018, 045125.

Ooi Chek Yee and Lim Soo King, Simulation study on the electrical performance of equilibrium thin-body double-gate nano-MOSFET, Jurnal Teknologi, 76(1), 2015, 87-95.

Ooi Chek Yee and Lim Soo King, Simulation study of 2D electron density in primed and unprimed subband thin-body double-gate nano-MOSFET of three different thicknesses and two temperature states, International Journal of Nanoelectronics and Materials, 9(1), 2016, 67-84.

Ooi Chek Yee and Lim Soo King, A comparative study of quantum gates and classical logic gates implemented using solid-state double-gate nano-MOSFETs, International Journal of Nanoelectronics and Materials, 9, 2016, 123-132.

Ooi Chek Yee and Wong Pei Voon, A flexibility and accuracy comparison study of different current-voltage equations for double-gate nano-MOSFET by simulation and theory, Applications of Modelling and Simulation, 5, 2021, 200-206.

Ooi Chek Yee, Device-circuit level simulation study of three inputs complex logic gate designed using nano-MOSFETs, Applications of Modelling and Simulation, 3(1), 2019, 1-10.

Ooi Chek Yee and Lim Soo King, Nano-MOSFETs implementation of different logic families of two inputs NAND gate transistor level circuits: a simulation study, Jurnal Teknologi, 79(7), 2017, 41-49.

Zhibin Ren, Nanoscale MOSFETs: Physics, Simulation and Design, Ph.D. Dissertation, Purdue University, 2001.

Ali Khakifirooz, Transport Enhancement Techniques for Nanoscale MOSFETs, Ph.D. Dissertation, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, 2008.

Raphael Clerc and Gerard Ghibaudo, Analytical models and electrical characterization of advanced MOSFETs in the quasi ballistic regime, International Journal of High Speed Electronics and Systems, 22(1), 2013, 1350002.

Vinod Kumar Khanna, Physics of carrier-transport mechanisms and ultra-small scale phenomena for theoretical modelling of nanometer MOS transistors from diffusive to ballistic regimes of operation, Physics Reports, 398, 2004, 67-131.

Ooi Chek Yee and Lim Soo King, Simulation study on different logic families of NOT gate transistor level circuits implemented using nano-MOSFETs, Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 8(5), 2016, 61-67.

Ooi Chek Yee, Mok Kai Ming and Wong Pei Voon, Device and circuit level simulation study of NOR gate logic families designed using nano-MOSFETs, Platform: A Journal of Science and Technology, 4(1), 2021, 73-84.

Ooi Chek Yee, Device and Transistor Level Circuit Performance Analysis of Nanoscale MOSFET, Ph.D. Dissertation, Lee Kong Chain Faculty of Engineering and Science, Universiti Tunku Abdul Rahman, Malaysia, 2019.

Rana Mahmoud, Narayanan Madathumpadical and Hasan Al-Nashash, TCAD simulation and analysis of selective buried oxide MOSFET dynamic power, Journal of Lower Power Electronics and Applications, 9, 2019, 29.

SangMin Woo, HyunJoon Jeong, JinYoung Choi, HyungMin Cho, Jeong-Taek Kong and SoYoung Kim, Machine-learning-based compact modeling for sub-3-nm emerging transistors, Electronics, 11, 2022, 2761.

Xufeng Wang, Nanomos 4.0: A Tool to Explore Ultimate Si Transistors and Beyond, Master of Science, Purdue University, 2010.

Cristina Medina-Bailon, Tapas Dutta, Ali Rezaei, Daniel Nagy, Fikru Adamu-Lema, Vihar P. Georgiev and Asen Asenov, Simulation and modeling of novel electronic device architectures with NESS (Nano-electronic simulation software): a modular nano TCAD simulation framework, Micromachines, 12, 2021, 680.

Zlatan Stanojevic, Chen-Ming Tsai, Georg Strof, Ferdinand Mitterbauer, Oskar Baumgartner, Christian Kernstock and Markus Karner, Nano device simulator – a practical subband-BTE solver for path-finding and DTCO, IEEE Transactions on Electron Devices, 68(11), 2021, 5400-5406.

Izwanizam Yahaya, A. H. Afifah Maheran, F. Salehuddin and K. E. Kaharudin, Design and electrical simulation of 22 nm MOSFET with graphene bilayer channel using double high-k metal gate, International Journal of Nanoelectronics and Materials, 15(2), 2022, 70-90.


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