Design of an ASIC Digital Clock Using VLSI Technology

Kim Ho Yeap, Yong Jun Tan, Yue Hong Chong, Siu Hong Loh, Jia Jia Sim, Ahmad Uzair Mazlan


We present the design of an Application Specific Integrated Circuit (ASIC) digital clock based on the 0.12 µm deep submicron technology node. The widths of the PMOS and NMOS transistors are 0.72 µm and 0.24 µm, respectively. The clock expresses time based on the 12-hour time notation. The gate-level schematic and the layout of the design are drawn and validated using DSCH3 and Microwind3 Lite. The key feature of the clock is constructed from 18 D-type flip-flops. Two modulo-60 counters and a modulo-12 counter are built from the flip-flops. The modulo-60 counters are used for the second and minute modules, while the modulo-12 flip-flop is for the hour module. The length and width of the layout are, respectively, 153.60 µm and 58.14 µm. This is to say that the size of the die is comparable with that of a human hair. The average static power dissipation is found to be 0.202 mW, which is reasonably low. Since the proposed design is in the form of an ASIC chip, the input and output pins merely require to be connected to an external power source, an oscillator, and displays, to allow the clock to operate properly. With its miniaturized size and low power consumption, the proposed design clearly exhibits advantages over those built using discrete components and general-purpose chips.


ASIC; Deep submicron technology; Digital clock; Modulus counter; VLSI.

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C. Stephens and M. Dennis, Engineering time: Inventing the electronic wristwatch, The British Journal for the History of Science, 33(4), 2000, 477-497.

K. H. Yeap, M. M. Isa and S. H. Loh, Introductory chapter: Integrated circuit chip, in Integrated Circuits / Microchips, 1st ed., K. H. Yeap and J. Sayago, Ed. UK.: Intech Open, 2020, 1-13.

K. H. Yeap, J. Y. Lee, W. L. Yeo, H. Nisar and S. H. Loh, Design and characterization of a 10 nm FinFET, Malaysian Journal of Fundamental and Applied Sciences, 15(4), 2019, 609-612.

K. H. Yeap, K. W. Thee, K. C. Lai, H. Nisar and K. C. Krishnan, VLSI circuit optimization for 8051 MCU, International Journal of Technology, 9(1), 2018, 142-149.

V. Misra, V. Pareek, V. K. Patel and M. K. Parashar, Digital clock using FND (fixed numeric digit) for temperature and humidity indicator, International Journal of Science and Research, 6(4), 2017, 747-750.

M. S. Raza and O. R. Zannat, Advanced design of smart digital application using PIC 16F887A microcontroller and DS 1307 RTC, American Journal of Embedded Systems and Applications, 6(1), 2018, 30-36.

D. C. Krishna and U. Sridevi, Displaying of digital clock through digital circuits and through assembly language programs of 8051 microcontroller, International Journal of Engineering Research and Application, 7(2), 2017, 1-6.

S. R. Khan, A. Kabir and D. A. Hossain, Designing smart multipurpose digital clock using real time clock (RTC) and PIC microcontroller, International Journal of Computer Applications, 41(9), 2012, 40-42.

Z. Ge, Y. Peng, Y. Zhang, S. Zhang and Z. Yang, Design of intelligent digital clock based on FPGA, Proceedings of International Conference on Wireless Communication, Network and Multimedia Engineering, Guilin, China, 2019, 198-200.

K. Win, A. N. Yakunin, A. M. San and N. L. Phyo, Digital clock with Myanmar digits, Proceedings of IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering, St. Petersburg and Moscow, Russia, 2020, 1978-1982.

R. Muley, B. Patil and R. Henry, Design and implementation of digital clock with stopwatch on FPGA, Proceedings of International Conference on Intelligent Computing and Control Systems, Madurai, India, 2017, 1033-1036.

N. K. Vuthuri, V. Mahewar, G. Yeddluri, E. S. Movva and V. Ch, A novel 7-segment digital clock implementation on FPGA, Proceedings of International Conference on Trends in Electronics and Informatics, Tirunelveli, India, 2017, 465-468.

S. R. K. Hudgikar and P. G. Kamble, A study on design and construction of a digital clock system, International Journal of Research and Analysis in Science and Engineering, 2(2), 2022, 37-44.

C. Zhang, Y. Liu, T. Jiang, W. Mao and J. Wang, Multisim-based digital clock design, Proceedings of Joint International Information Technology and Artificial Intelligence Conference, Chongqing, China, 2020, 1906-1911.

B. Macfadden, Hair Culture: Rational Methods for Growing the Hair and for Developing Its Strength and Beauty. Applewood Books, Bedford: Massachusetts, 2000.


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